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Hex-Half-Bridge / Double Six-Driver
Data Sheet 1 1.1 * * * * * * * * * * * * * * Overview Features
TLE 6208-6 G
SPT 4
Six High-Side and six Low-Side-Drivers Free configurable as switch, halfbridge or H-bridge Optimized for DC motor management applications 0.6 A continuous (1 A peak) current per switch RDS ON; typ. 0.8 , @ 25 C per switch Outputs fully short circuit protected with diagnosis Overtemperature-Protection with hysteresis and diagnosis Temperature prewarning Standard SPI-Interface Very low current consumption (typ. 10 A, @ 25 C) in stand-by (Inhibit) mode Over- and Undervoltage-Lockout CMOS/TTL compatible inputs with hysteresis Internal clamp diodes Enhanced power P-DSO-Package Ordering Code Q67007-A9462
P-DSO-28-6 Enhanced Power
Type TLE 6208-6 G Functional Description
Package P-DSO-28-6
The TLE 6208-6 G is a fully protected Hex-Half-Bridge-Driver designed specifically for automotive and industrial motion control applications. The part is based on Infineons Smart Power Technology SPT(R) which allows bipolar and CMOS control circuitry in accordance with DMOS power devices existing on the same monolithic circuitry. The six low and high side drivers are freely configurable and can be controlled separately. Therefore all kind of loads can be combined. In motion control up to 5 actuators (DCMotors) can be connected to the 6 halfbridge-outputs (cascade configuration). Operation modes forward (cw), reverse (ccw), brake and high impedance are controlled from a standard SPI-Interface. The possibility to control the outputs via software from a central logic, allows limiting the power dissipation. So the standard P-DSO-28-6-package meets the application requirements and saves PCB-Board-space and cost. Furthermore the build-in features like Over- and Undervoltage-Lockout, OverTemperature-Protection and the very low quiescent current in stand-by mode opens a wide range of automotive- and industrial-applications.
Data Sheet 1 2001-11-15
TLE 6208-6 G
1.2
Pin Configuration (top view) P-DSO-28-6
Figure 1
Data Sheet
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TLE 6208-6 G
1.3 Pin No. 1
Pin Definitions and Functions Symbol OUTL5 Function Low-Side-Output 5; Power-MOS open drain with internal reverse diode; no internal clamp diode or active zenering; short circuit protected and open load controlled. High-Side-Output 5; Power-MOS open source with internal reverse diode; no internal clamp diode or active zenering; short circuit protected and open load controlled. High-Side-Output 4; see pin2. Low-Side-Output 4; see pin1. Power supply; external connection to pin 10 necessary; needs a blocking capacitor as close as possible to GND Value: 22 F electrolytic in parallel to 220 nF ceramic. Ground; Reference potential; internal connection to pin 20, 21, 22 and 23; cooling tab; to reduce thermal resistance; place cooling areas on PCB close to this pins. Power Supply; see pin 5. Low-Side-Output 3; see pin1. High-Side-Output 3; see pin2. High-Side-Output 2; see pin2. Low-Side-Output 2; see pin1. High-Side-Output 1; see pin2. Low-Side-Output 1; see pin1. Inhibit input; has an internal pull down; device is switched in standby condition by pulling the INH terminal low. Serial-Data-Output; this 3-state output transfers diagnosis data to the control device; the output will remain 3-stated unless the device is selected by a low on Chip-Select-Not (CSN); see Table 2 for Diagnosis protocol. Logic supply voltage; needs a blocking capacitor as close as possible to GND; Value: 10 F electrolytic in parallel to 220 nF ceramic.
2
OUTH5
3 4 5
OUTH4 OUTL4
VS
6, 7, 8, 9 GND
10 11 12 13 14 15 16 17
VS
OUTL3 OUTH3 OUTH2 OUTL2 OUTH1 OUTL1 INH
18
DO
19
VCC
Data Sheet
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TLE 6208-6 G
1.3 Pin No. 20, 21, 22, 23 24
Pin Definitions and Functions (cont'd) Symbol GND CSN Function Ground Chip-Select-Not input; CSN is an active low input; serial communication is enabled by pulling the CSN terminal low; CSN input should only be transitioned when CLK is low; CSN has an internal active pull up and requires CMOS logic level inputs. Serial clock input; clocks the shiftregister; CLK has an internal active pull down and requires CMOS logic level inputs. Serial data input; receives serial data from the control device; serial data transmitted to DI is an 16bit control word with the Least Significant Bit (LSB) being transferred first: the input has an active pull down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see Table 1 for input data protocol. Low-Side-Output 6; see pin1. High-Side-Output 6; see pin2.
25 26
CLK DI
27 28
OUTL6 OUTH6
Data Sheet
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TLE 6208-6 G
1.4
Functional Block Diagram
Figure 2 Block Diagram
Data Sheet
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TLE 6208-6 G
1.5
Circuit Description
Figure 2 shows a block schematic diagram of the module. There are 6 halfbridge drivers on the right-hand side. An HS driver and an LS driver are combined to form a halfbridge driver in each case. The drivers communicate via the internal data bus with the logic and the other control and monitoring functions: undervoltage (UV), overvoltage (OV), overtemperature (TSD), charge pump and fault detect. Two connection interfaces are provided for supply to the module: All power drivers are connected to the supply voltage VS. These are monitored by overvoltage and undervoltage comparators with hysteresis, so that the correct function can be checked in the application at any time. The logic is supplied by the VCC voltage, typ. with 5 V. The VCC voltage uses an internally generated Power-On Reset (POR) to initialize the module at power-on. The advantage of this system is that information stored in the logic remains intact in the event of shortterm failures in the supply voltage VS. The system can therefore continue to operate following VS undervoltage, without having to be reprogrammed. The "undervoltage" information is stored, and can be read out via the interface. The same logically applies for overvoltage. "Interference spikes" on VS are therefore effectively suppressed. The situation is different in the case of undervoltage on the VCC connection pin. If this occurs, then the internally stored data is deleted, and the output levels are switched to high-impedance status (tristate). The module is initialized by VCC following restart (Power-On Reset = POR). The 16-bit wide programming word or control word (see Table 1) is read in via the DI data input, and this is synchronized with the clock input CLK. The status word appears synchronously at the DO data output (see Table 2). The transmission cycle begins when the chip is selected with the CSN input (H to L). If the CSN input changes from L to H then the word which has been read in becomes the control word. The DO output switches to tristate status at this point, thereby releasing the DO bus circuit for other uses. The INH inhibit input can be used to cut off the complete module. This reduces the current consumption to just a few A, and results in the loss of any data stored. The output levels are switched to tristate status. The module is reinitialized with the internally generated POR (Power-On Reset) at restart. This feature allows the use of this module in battery-operated applications (vehicle body control applications). Every driver block from DRV 1 to 6 contains a low-side driver and a high-side driver. The output connections have been selected so that each HS driver and LS driver pair can be combined to form a halfbridge by short-circuiting adjacent connections. The full flexibility of the configuration can be achieved by dissecting the halfbridges into "quarter-bridges". Table 3 shows examples of possible applications.
Data Sheet 6 2001-11-15
TLE 6208-6 G
When commutating inductive loads, the dissipated power peak can be significantly reduced by activating the transistor located parallel to the internal freewheeling diode. A special, integrated "timer" for power ON/OFF times ensures there is no crossover current at the halfbridge.
Figure 3 Configuration Examples for "Quarter Bridges" on the TLE 6208-6 G
Data Sheet
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TLE 6208-6 G
Table 1 Input Data Protocol BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H = ON L = OFF OVLO on/off Underload SD on/off Overcurrent SD on/off HS-Switch 6 LS-Switch 6 HS-Switch 5 LS-Switch 5 HS-Switch 4 LS-Switch 4 HS-Switch 3 LS-Switch 3 HS-Switch 2 LS-Switch 2 HS-Switch 1 LS-Switch 1 Status Register Reset
Table 2 Diagnosis Data Protocol BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H = ON L = OFF Power supply fail Underload Overload Status HS-Switch 6 Status LS-Switch 6 Status HS-Switch 5 Status LS-Switch 5 Status HS-Switch 4 Status LS-Switch 4 Status HS-Switch 3 Status LS-Switch 3 Status HS-Switch 2 Status LS-Switch 2 Status HS-Switch 1 Status LS-Switch 1 Temp. Prewarning
Data Sheet
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TLE 6208-6 G
Table 3 Fault Result Table Fault Overcurrent (load) Diag.-Bit 13 Result Only the failed output is switched OFF. Function and protection can be deactivated by bit No. 13. Only the failed output is switched OFF. Function and protection can be deactivated by bit No. 13. Only the failed output is switched OFF. Function and protection can be deactivated by bit No. 13. Reaction of control device needed. All outputs OFF. Only the failed output is switched OFF. Function can be deactivated by bit No. 14. Only the failed output is switched OFF. Function can be deactivated by bit No. 14. All outputs OFF. All outputs OFF. Function can be deactivated by bit No. 15.
Short circuit to GND (high-side-switch) Short circuit to VS (low-side-switch)
13
13
Temperature warning 0 Temperature shut down (SD) Openload Underload - 14 14
Undervoltage lockout 15 (UVLO) Overvoltage lockout (OVLO) H = failure; L = no failure. 15
Data Sheet
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TLE 6208-6 G
2 2.1
Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values min. max. Unit Remarks
Parameter
Voltages Supply voltage Supply voltage Logic supply voltage Logic input voltages (DI, CLK, CSN, INH) Logic output voltage (DO) Currents Output current (cont.), if Bit13 (OCSD) is set.
VS VS VCC VI VDO
- 0.3 -1 - 0.3 - 0.3 - 0.3
40 - 5.5 5.5
V V V V V
-
VCC
t < 0.5 s; IS > - 2 A 0 V < VS < 40 V 0 V < VS < 40 V 0 V < VCC < 5.5 V 0 V < VS < 40 V 0 V < VCC < 5.5 V
IOUT1-6
- - 1.5 - 0.7 - -2 - 0.9 - 0.3
- 1.5 0.7 - 2 0.9 0.3
A A A A A A A A
internal limited
IOUT1-6 Output current (cont.), if Bit13 (OCSD) is deactivated.
Output current (peak), if Bit13 (OCSD) is set.
- 0.25 0.25
VDS = 12 V VDS = 20 V VDS = 40 V
internal limited
IOUT1-6
IOUT1-6 Output current (peak), if Bit13 (OCSD) is deactivated. tP < 50 ms; t = 1 s;
Temperatures Junction temperature Storage temperature
VDS = 12 V VDS = 20 V VDS = 40 V
Tj Tstg
- 40 - 50
150 150
C C
- -
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.
Data Sheet
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TLE 6208-6 G
2.2
Operating Range Symbol Limit Values min. max. V V/s V After VS rising above VUV ON - - Outputs in tristate Outputs in tristate - - - Unit Remarks
Parameter Supply voltage Supply voltage slew rate Logic supply voltage Supply voltage increasing Supply voltage decreasing Logic input voltage (DI, CLK, CSN, INH) SPI clock frequency Junction temperature Thermal Resistances Junction pin Junction ambient
VS
dVS /dt
VUV OFF 40
- 4.75 - 0.3 - 0.3 - 0.3 - - 40 10 5.50
VCC VS VS VI fCLK Tj
VUV ON V VUV OFF V VCC V
2 150 MHz C
Rthj-pin RthjA
- -
25 65
K/W K/W
measured to pin 7 -
Data Sheet
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TLE 6208-6 G
2.3
Electrical Characteristics
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; - 40 C < Tj < 150 C; unless otherwise specified
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Current Consumption Quiescent current
IS
-
10
20
A
INH = Low;
VS = 13.2 V; Tj = 25 C
INH = Low; VS = 13.2 V - INH = Low SPI not active
Quiescent current Supply current Logic-Supply current Logic-Supply current
IS IS ICC ICC
- - - -
- 2.0 2 1.6
40 4.0 10 3.0
A mA A mA
Over- and Under-Voltage Lockout UV-Switch-ON voltage UV-Switch-OFF voltage UV-ON/OFF-Hysteresis OV-Switch-OFF voltage OV-Switch-ON voltage OV-ON/OFF-Hysteresis
VUV ON VUV OFF VUV HY VOV OFF VOV ON VOV HY
- 5.5 - 34 28 -
6.5 6.0 0.5 37 32 5.0
7.0 6.6 - 40 36 -
V V V V V V
VS increasing VS decreasing VUV ON - VUV OFF VS increasing VS decreasing VOV OFF - VOV ON
Data Sheet
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TLE 6208-6 G
2.3
Electrical Characteristics (cont'd)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; - 40 C < Tj < 150 C; unless otherwise specified
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Outputs OUTH1-6 and OUTL1-6 Static Drain-Source-On Resistance Source (High-Side) IOUT = - 0.5 A
RDS ON H
-
0.9 - 2.0 -
1.3 2.0 - 4.0 1.2 2.0 - 4.0

Sink (Low-Side) IOUT = 0.5 A
RDS ON L
-
0.8 - 2.0 -
8 V < VS < 40 V Tj = 25 C 8 V < VS < 40 V VS OFF < VS 8 V Tj = 25 C VS OFF < VS 8 V 8 V < VS < 40 V Tj = 25 C 8 V < VS < 40 V VS OFF < VS 8 V Tj = 25 C VS OFF < VS 8 V
Note: Values of RDS ON for VS OFF < VS 8 V are guaranteed by design. Leakage Current Source-Output-Stage 1 to 6 Source-Output-Stage 1 to 6 Sink-Output-Stage 1 to 6 Sink-Output-Stage 1 to 6
IQLH IQLH IQLL IQLL
-1 -5 - -
- - - -
- - 1 5
A A A A
VOUTH1-6 = 0 V Tj = 25 C VOUTH1-6 = 0 V VOUTL1-6 = VS Tj = 25 C VOUTL1-6 = VS
Data Sheet
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TLE 6208-6 G
2.3
Electrical Characteristics (cont'd)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; - 40 C < Tj < 150 C; unless otherwise specified
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Overcurrent Source shutdown threshold Sink shutdown threshold Current limit Shutdown delay time Open Circuit Detection current Delay time
ISDU ISDL IOCL tdSD
- 2.0 - 1.5 - 1.0 A 1.0 - 10 1.5 3.0 25 2.0 5.0 50 A A s
- - sink and source sink and source
IOCD tdOC
15 200
30 350
50 600
mA s
- -
Delay Time from Stand-by to Data In Setup time
tset
-
-
100
s
-
Note: setup time is guarnteed by design Output Delay Times; VS = 13.2 V; RLoad = 25 (device not in stand-by for t > 1 ms) Source (high-side) ON Source (high-side) OFF Sink (low-side) ON Sink (low-side) OFF Dead time H to L Dead time L to H
td ON H td OFF H td ON L td OFF L tD HL tD LH
- - - - 1.5 2.5
7.5 3 6.5 2 - -
12 6 12 5 - -
s s s s s s
- - - -
td ON L - td OFF H td ON H - td OFF L
Data Sheet
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TLE 6208-6 G
2.3
Electrical Characteristics (cont'd)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; - 40 C < Tj < 150 C; unless otherwise specified
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Output Switching Times; VS = 13.2 V; RLoad = 25 (device not in stand-by for t > 1 ms) Source (high-side) rise-time Source (high-side) fall-time Sink (low-side) fall-time Sink (low-side) rise-time
tON H tOFF H tON L tOFF L
- - - -
4 2 1 1
8 3 3 2
s s s s
- - - -
Clamp Diodes Forward Voltage Upper Lower Inhibit Input H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Pull down current Input capacitance
VFU VFL
- -
0.9 0.9
1.3 1.3
V V
IF = 0.5 A IF = 0.5 A
VIH VIL VIHY II CI
- 0.2 50 10 -
- - 200 25 10
0.7 - 500 50 15
VCC VCC
mV A pF
- - -
VI = 0.2 x VCC 0 V < VCC <
5.25 V
Note: Capacitances are guaranteed by design
Data Sheet
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TLE 6208-6 G
2.3
Electrical Characteristics (cont'd)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; - 40 C < Tj < 150 C; unless otherwise specified
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
SPI-Interface Delay Time from Stand-by to Data In Setup time
tset
-
-
100
s
-
Logic Inputs DI, CLK and CSN H-input voltage threshold
VIH VIL L-input voltage threshold Hysteresis of input voltage VIHY IICSN Pull up current at pin CSN Pull down current at pin DI IIDI Pull down current at pin CLK IICLK Input capacitance CI
at pin CSN, DI or CLK
- 0.2 50 - 50 10 10 -
- - 200 - 25 25 25 10
0.7 - 500 - 10 50 50 15
VCC VCC
mV A A A pF
- - -
VCSN = 0.7 x VCC VDI = 0.2 x VCC VCLK = 0.2 x VCC 0 V < VCC <
5.25 V
Note: Capacitances are guaranteed by design Logic Output DO H-output voltage level L-output voltage level Tri-state leakage current Tri-state input capacitance
VDOH VDOL IDOLK CDO
VCC
- - 10 -
VCC
0.2 - 10
- 0.4 10 15
V V A pF
IDOH = 1 mA IDOL = - 1.6 mA VCSN = VCC 0 V < VDO < VCC VCSN = VCC 0 V < VCC <
5.25 V
- 1.0 - 0.7
Note: Capacitances are guaranteed by design
Data Sheet
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TLE 6208-6 G
2.3
Electrical Characteristics (cont'd)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; - 40 C < Tj < 150 C; unless otherwise specified
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Data Input Timing Clock period Clock high time Clock low time Clock low before CSN low CSN setup time CLK setup time Clock low after CSN high DI setup time DI hold time Input signal rise time at pin DI, CLK and CSN Input signal fall time at pin DI, CLK and CSN Data Output Timing DO rise time DO fall time DO enable time DO disable time DO valid time
tpCLK tCLKH tCLKL tbef tlead tlag tbeh tDISU tDIHO trIN tfIN
1000 500 500 500 500 500 500 250 250 - -
- - - - - - - - - - -
- - - - - - - - - 200 200
ns ns ns ns ns ns ns ns ns ns ns
- - - - - - - - - - -
trDO tfDO tENDO tDISDO tVADO
- - - - -
50 50 - - 100
100 100 250 250 250
ns ns ns ns ns
CL = 100 pF CL = 100 pF
low impedance high impedance
VDO < 0.2 VCC; VDO > 0.7 VCC; CL = 100 pF
Data Sheet
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TLE 6208-6 G
2.3
Electrical Characteristics (cont'd)
8 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; all outputs open; - 40 C < Tj < 150 C; unless otherwise specified
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Thermal Prewarning and Shutdown Thermal prewarning junction TjPW temperature Temperature prewarning hysteresis Thermal shutdown junction temperature Thermal switch-on junction temperature Temperature shutdown hysteresis Ratio of SD to PW temperature T 120 - 150 120 - 1.05 145 30 175 - 30 1.20 170 - 200 170 - - C K C C K - - - - - - -
TjSD TjSO
T
TjSD / TjPW
Note: Temperatures are guaranteed by design
Data Sheet
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TLE 6208-6 G
3
Timing Diagrams
CSN High to Low & rising edge of CLK: DO is enabled. Status information is transfered to Output Shift Register
CSN time CSN Low to High: Data from Shift-Register is transfered to Output Power Switches
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
actual Data DI 0 1 2 3 4 5 _ 6 7 8 9 10 11 12 13 14 15
new Data 0 + 1 +
DI: Data will be accepted on the falling edge of CLK-Signal previous Status DO _ 0 _ 1 _ 2 _ 3 4 _ _ 5 _ 6 _ 7 _ 8 _ 9 10 _ _ 11 12 _ 13 _ 14 _ 15 _ actual Status 0 1
DO: State will change on the rising edge of CLK-Signal
eg. HS1
old Data
actual Data
Figure 4 Standard Data Transfer Timing
CSN High to Low & CLK stays Low: Status information of Data Bit 0 ( Temperature prewarning ) is transfered to DO CSN time
CLK
DI DI: Data is not accepted
DO
_ 0 DO: Status information of Data Bit 0 ( Temperature prewarning ) will stay as long as CSN is low
Figure 5 Timing for Temperature Prewarning only
Data Sheet 19 2001-11-15
TLE 6208-6 G
Figure 6 SPI-Input Timing
trIN
tfIN 70 %
CSN
50 % 20 % tdOFF
Case 1 IOUT
90%
ON State
OFF State
50 % 10 %
tdON
tOFF tON 90 %
Case 2 IOUT
OFF State
ON State
50 % 10 %
Figure 7 Turn OFF/ON Time
Data Sheet 20 2001-11-15
TLE 6208-6 G
trIN
tfIN 0.7 VCC
CLK
trDO
50 % 0.2 VCC
0.7 VCC
DO
( low to high )
0.2 VCC tVADO tfDO 0.7 VCC
DO
( high to low )
0.2 VCC
Figure 8 DO Valid Data Delay Time and Valid Time
tfIN trIN 0.7 VCC
CSN
tENDO tDISDO 10 k Pullup to VCC
50 % 0.2 VCC
DO
50 %
tENDO
tDISDO 10 k Pulldown 50 % to GND
DO
Figure 9 DO Enable and Disable Time
Data Sheet
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TLE 6208-6 G
4
Application
Figure 10 Application Circuit
Data Sheet
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TLE 6208-6 G
5
Package Outlines P-DSO-28-6 (Plastic Dual Small Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Data Sheet 23
Dimensions in mm 2001-11-15
GPS05123

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